An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete. The canonical simulator of VHDL is enriched by new mechanisms, the predefined environment is more complete, and the syntax is more regular and flexible. Discrepancies and known bugs of VHDL'87 have been fixed. However, the new VHDL'92 is compatible with VHDL'87, with some minor exceptions. This book presents the new VHDL'92 for the VHDL designer. New features ar explained and classified. Examples are provided, each new feature is given a rationale and its impact on design methodology, and performance is analysed. Where appropriate, pitfalls and traps are explained. The VHDL designer will quickly be able to find the feature needed to evaluate the benefits it brings, to modify previous VHDL'87 code to make it more efficient, more portable, and more flexible. VHDL'92 is the essential update for all VHDL designers and managers involved in electronic design.
| Autorius: | Jean-Michel Bergé, Jacques Rouillard, Serge Maginot, Alain Fonkoua, |
| Serija: | The Springer International Series in Engineering and Computer Science |
| Leidėjas: | Springer New York |
| Išleidimo metai: | 2012 |
| Knygos puslapių skaičius: | 236 |
| ISBN-10: | 1461364272 |
| ISBN-13: | 9781461364276 |
| Formatas: | 235 x 155 x 13 mm. Knyga minkštu viršeliu |
| Kalba: | Anglų |
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