Design Of High Speed and Low Power Multiplier

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48,81 
Įprasta kaina: 57,42 
-15% su kodu: ENG15
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Akcija baigiasi: 2025-03-03
-15% su kodu: ENG15
48,81 
Įprasta kaina: 57,42 
-15% su kodu: ENG15
Kupono kodas: ENG15
Akcija baigiasi: 2025-03-03
-15% su kodu: ENG15
2025-02-28 57.4200 InStock
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Knygos aprašymas

Power dissipation is recognized as a critical parameter in modern VLSI field. To produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary.The increasing speed and complexity of today¿s designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. Multiplication is an important part of real-time digital signal processing (DSP) applications ranging from digital filtering to image processing.The Spurious Power Suppression Technique (SPST) uses a detection logic circuit to detect the effective data range of arithmetic units.

Informacija

Autorius: S. Gopalakrishnan, G. Sasi,
Leidėjas: LAP LAMBERT Academic Publishing
Išleidimo metai: 2019
Knygos puslapių skaičius: 56
ISBN-10: 6139461340
ISBN-13: 9786139461349
Formatas: 220 x 150 x 4 mm. Knyga minkštu viršeliu
Kalba: Anglų

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