ASIC Implementation of Low Power FP-AU using Reversible Logic: Floating Point (FP)-Arithmetic Units (AU)

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Įprasta kaina: 51,68 
-15% su kodu: ENG15
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Akcija baigiasi: 2025-03-03
-15% su kodu: ENG15
43,93 
Įprasta kaina: 51,68 
-15% su kodu: ENG15
Kupono kodas: ENG15
Akcija baigiasi: 2025-03-03
-15% su kodu: ENG15
2025-02-28 51.6800 InStock
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Knygos aprašymas

This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.

Informacija

Autorius: Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram, Vinoth Kumar Bojan,
Leidėjas: LAP LAMBERT Academic Publishing
Išleidimo metai: 2018
Knygos puslapių skaičius: 52
ISBN-10: 6139587050
ISBN-13: 9786139587056
Formatas: 220 x 150 x 4 mm. Knyga minkštu viršeliu
Kalba: Anglų

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