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This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
| Autorius: | Vaibbhav Taraate |
| Leidėjas: | Springer Nature Singapore |
| Išleidimo metai: | 2021 |
| Knygos puslapių skaičius: | 352 |
| ISBN-10: | 9813346418 |
| ISBN-13: | 9789813346413 |
| Formatas: | 241 x 160 x 25 mm. Knyga kietu viršeliu |
| Kalba: | Anglų |
Parašykite atsiliepimą apie „ASIC Design and Synthesis: RTL Design Using Verilog“
