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As the MOSFET dimensions scale down to nanoscale level, the reliability of circuits based on these devices decreases. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal noise sources to provide a more rigorous noise environment for the simulation of nanoscale circuits. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The re-designed MRF is termed as Improved-MRF. By simulating various test circuits in Cadence, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives.
| Autorius: | Jahanzeb Anwer, Nor Hisham Bin Hamid, Vijanth Sagayan Asirvadam, |
| Leidėjas: | LAP LAMBERT Academic Publishing |
| Išleidimo metai: | 2011 |
| Knygos puslapių skaičius: | 88 |
| ISBN-10: | 3844332634 |
| ISBN-13: | 9783844332636 |
| Formatas: | 220 x 150 x 6 mm. Knyga minkštu viršeliu |
| Kalba: | Anglų |
Parašykite atsiliepimą apie „An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs“
