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This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
| Autorius: | Vaibbhav Taraate |
| Leidėjas: | Springer Nature Singapore |
| Išleidimo metai: | 2019 |
| Knygos puslapių skaičius: | 332 |
| ISBN-10: | 981108775X |
| ISBN-13: | 9789811087752 |
| Formatas: | 241 x 160 x 24 mm. Knyga kietu viršeliu |
| Kalba: | Anglų |
Parašykite atsiliepimą apie „Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog“
