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Zeljko Zilic

Rasta: 4
Verification by Error Modeling: Using Testing Techniques in Hardware Verification
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Verification by Error Modeling: Using Testing Techniques in Hardware Verification
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Accelerating Test, Validation and Debug of High Speed Serial Interfaces
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Rasta: 4