Shivani Madhok

Rasta: 1
Energy Efficient Design Techniques On FPGA: Low power Design Goal with Capacitance Scaling, Thermal Aware, HSTL, SSTL & LVCMOS IO Standard and Frequency Scaling
-15% su kodu: ENG15
75,74 
89,10 
Išsiųsime per 11-15 d. d.
Rasta: 1