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Alberto L. Sangiovanni-Vincentelli

Rasta: 20
Synthesis of Finite State Machines: Functional Optimization
-15% su kodu: ENG15
215,97 
254,08 
Išsiųsime per 11-15 d. d.
Synchronous Equivalence: Formal Methods for Embedded Systems
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Function/Architecture Optimization and Co-Design of Embedded Systems
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Logic Synthesis for Field-Programmable Gate Arrays
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Synthesis of Finite State Machines: Logic Optimization
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Steady-State Methods for Simulating Analog and Microwave Circuits
-15% su kodu: ENG15
316,76 
372,66 
Išsiųsime per 11-15 d. d.
Algorithms for Synthesis and Testing of Asynchronous Circuits
-15% su kodu: ENG15
316,76 
372,66 
Išsiųsime per 11-15 d. d.
Logic Minimization Algorithms for VLSI Synthesis
-15% su kodu: ENG15
259,17 
304,90 
Išsiųsime per 11-15 d. d.
Noise Analysis of Radio Frequency Circuits
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Steady-State Methods for Simulating Analog and Microwave Circuits
-15% su kodu: ENG15
316,76 
372,66 
Išsiųsime per 11-15 d. d.
Synthesis of Finite State Machines: Functional Optimization
-15% su kodu: ENG15
215,97 
254,08 
Išsiųsime per 11-15 d. d.
Synthesis of Finite State Machines: Logic Optimization
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Synchronous Equivalence: Formal Methods for Embedded Systems
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Logic Synthesis for Field-Programmable Gate Arrays
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Algorithms for Synthesis and Testing of Asynchronous Circuits
-15% su kodu: ENG15
316,76 
372,66 
Išsiųsime per 11-15 d. d.
Function/Architecture Optimization and Co-Design of Embedded Systems
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Relaxation Techniques for the Simulation of VLSI Circuits
-15% su kodu: ENG15
143,97 
169,38 
Išsiųsime per 11-15 d. d.
Logic Minimization Algorithms for VLSI Synthesis
-15% su kodu: ENG15
259,17 
304,90 
Išsiųsime per 11-15 d. d.
Rasta: 20